diff --git a/FresseHalten/FresseHalten.sch b/FresseHalten/FresseHalten.sch
deleted file mode 100644
index 0b42434..0000000
--- a/FresseHalten/FresseHalten.sch
+++ /dev/null
@@ -1,697 +0,0 @@
-
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-<b>FEMALE PRINT CONNECTOR</b><p>
-DIN 45323 (34V/3A), ROKA, distributor Conrad
-
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-ABK-PRO-MINI
-
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-<b>SMALL OUTLINE TRANSISTOR</b><p>
-reflow soldering
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-<b>MOLEX 2.54mm KK RA CONNECTOR</b>
-<br>Fixed Orientation
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->NAME
-1
-3
->VALUE
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-<b>MOLEX 2.54mm KK CONNECTOR</b>
-
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->NAME
-1
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-<b>VOLTAGE REGULATOR</b>
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->NAME
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-A15,2mm
--
-I
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->NAME
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-+
--
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-ABK-Pro-Mini
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-Arduino Pro Mini
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->VALUE
->NAME
-D
-S
-G
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->VALUE
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->NAME
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->VALUE
-GND
-IN
-OUT
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-ABK Pro-Mini Arduino Clone
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-MOSFET N-Channel 20 V (D-S)
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-<b>Serie 733, Stiftleiste (für Leiterplatten) Einlötstift abgewinkelt 0,8 x 0,8 mm / Series 733, Male header (for PCBs) Angled solder pin 0.8 x 0.8 mm</b><br><br>Polzahl / Pole No.: 4 <br>Rastermaß / Pitch: 2.5 - 2.5 mm<br>Bemessungsspannung / Rated Voltage: 160 V<br>Nennstrom / Nominal Current: 6 A<br>Lötstiftlänge: / Solder Pin Length: 3.7 mm<br>Farbe / Color: lichtgrau / light gray<br><br> Stand: 01.01.2014. Die jeweils aktuellen Daten zu diesem Artikel finden Sie in unserem Produktkatalog, den Sie unter <a href="http://www.wago.com">www.wago.com</a> einsehen können. <br> As of: 01/01/2014. Please find the newest data for this article in our product catalogue, which can be viewed under <a href="http://www.wago.com">www.wago.com</a>.<br>
-
-
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-<b>CONNECTOR</b><p>
-wire to board 2.54 mm (.1 inch) pitch header
-
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-<b>VOLTAGE REGULATOR</b>
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diff --git a/KlighD Examples/KlighD Examples.lbr b/KlighD Examples/KlighD Examples.lbr
new file mode 100644
index 0000000..2cc1bda
--- /dev/null
+++ b/KlighD Examples/KlighD Examples.lbr
@@ -0,0 +1,310 @@
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+1
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+>NAME
+>VALUE
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+<b>PHOENIX</b>
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+>NAME
+>VALUE
+1
+2
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+>NAME
+>VALUE
+GND
+IN
+OUT
+
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+>VALUE
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+>NAME
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+>VALUE
+>NAME
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+<b>SUPPLY SYMBOL</b>
+
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+<b>PHOENIX</b>
+
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+<b>SUPPLY SYMBOL</b>
+
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+
diff --git a/KlighD Examples/VoltageRegulation.sch b/KlighD Examples/VoltageRegulation.sch
new file mode 100644
index 0000000..aef7bee
--- /dev/null
+++ b/KlighD Examples/VoltageRegulation.sch
@@ -0,0 +1,371 @@
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+<b>PHOENIX</b>
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+>NAME
+>VALUE
+1
+2
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+1
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+>NAME
+>VALUE
+
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+>NAME
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+>VALUE
+>NAME
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+
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+>NAME
+>VALUE
+GND
+IN
+OUT
+
+
+
+
+
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+>VALUE
+
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+>VALUE
+
+
+
+
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+<b>PHOENIX</b>
+
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+<b>SUPPLY SYMBOL</b>
+
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+<b>SUPPLY SYMBOL</b>
+
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diff --git a/LED5050-Control-v2/OSHParkDesignRules.dru b/LED5050-Control-v2/OSHParkDesignRules.dru
deleted file mode 100644
index 31e694d..0000000
--- a/LED5050-Control-v2/OSHParkDesignRules.dru
+++ /dev/null
@@ -1,73 +0,0 @@
-description[de] = EAGLE Design Rules\n\nDie Standard-Design-Rules sind so gewählt, dass sie für \ndie meisten Anwendungen passen. Sollte ihre Platine \nbesondere Anforderungen haben, treffen Sie die erforderlichen\nEinstellungen hier und speichern die Design Rules unter \neinem neuen Namen ab.
-description[en] = Laen's PCB Order Design Rules\n
\nPlease make sure your boards conform to these design rules.
-layerSetup = (1*16)
-mtCopper = 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm
-mtIsolate = 1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm
-mdWireWire = 6mil
-mdWirePad = 6mil
-mdWireVia = 6mil
-mdPadPad = 6mil
-mdPadVia = 6mil
-mdViaVia = 6mil
-mdSmdPad = 6mil
-mdSmdVia = 6mil
-mdSmdSmd = 6mil
-mdViaViaSameLayer = 8mil
-mnLayersViaInSmd = 2
-mdCopperDimension = 15mil
-mdDrill = 6mil
-mdSmdStop = 0mil
-msWidth = 6mil
-msDrill = 13mil
-msMicroVia = 13mil
-msBlindViaRatio = 0.500000
-rvPadTop = 0.250000
-rvPadInner = 0.250000
-rvPadBottom = 0.250000
-rvViaOuter = 0.250000
-rvViaInner = 0.250000
-rvMicroViaOuter = 0.250000
-rvMicroViaInner = 0.250000
-rlMinPadTop = 7mil
-rlMaxPadTop = 20mil
-rlMinPadInner = 7mil
-rlMaxPadInner = 20mil
-rlMinPadBottom = 7mil
-rlMaxPadBottom = 20mil
-rlMinViaOuter = 7mil
-rlMaxViaOuter = 20mil
-rlMinViaInner = 7mil
-rlMaxViaInner = 20mil
-rlMinMicroViaOuter = 4mil
-rlMaxMicroViaOuter = 20mil
-rlMinMicroViaInner = 4mil
-rlMaxMicroViaInner = 20mil
-psTop = -1
-psBottom = -1
-psFirst = -1
-psElongationLong = 100
-psElongationOffset = 100
-mvStopFrame = 1.000000
-mvCreamFrame = 0.000000
-mlMinStopFrame = 3mil
-mlMaxStopFrame = 3mil
-mlMinCreamFrame = 0mil
-mlMaxCreamFrame = 0mil
-mlViaStopLimit = 0mil
-srRoundness = 0.000000
-srMinRoundness = 0mil
-srMaxRoundness = 0mil
-slThermalGap = 0.500000
-slMinThermalGap = 20mil
-slMaxThermalGap = 100mil
-slAnnulusIsolate = 20mil
-slThermalIsolate = 10mil
-slAnnulusRestring = 0
-slThermalRestring = 1
-slThermalsForVias = 0
-checkGrid = 0
-checkAngle = 0
-checkFont = 1
-checkRestrict = 1
-useDiameter = 13
-maxErrors = 50
diff --git a/LED5050-Control/OSHParkDesignRules.dru b/Lighthouse/ITead_rule.dru
similarity index 58%
rename from LED5050-Control/OSHParkDesignRules.dru
rename to Lighthouse/ITead_rule.dru
index 31e694d..8cc01ca 100644
--- a/LED5050-Control/OSHParkDesignRules.dru
+++ b/Lighthouse/ITead_rule.dru
@@ -1,73 +1,74 @@
-description[de] = EAGLE Design Rules\n
\nDie Standard-Design-Rules sind so gewählt, dass sie für \ndie meisten Anwendungen passen. Sollte ihre Platine \nbesondere Anforderungen haben, treffen Sie die erforderlichen\nEinstellungen hier und speichern die Design Rules unter \neinem neuen Namen ab.
-description[en] = Laen's PCB Order Design Rules\n
\nPlease make sure your boards conform to these design rules.
-layerSetup = (1*16)
-mtCopper = 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm 0.0356mm
-mtIsolate = 1.5011mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm 0.1499mm 0.2007mm
-mdWireWire = 6mil
-mdWirePad = 6mil
-mdWireVia = 6mil
-mdPadPad = 6mil
-mdPadVia = 6mil
-mdViaVia = 6mil
-mdSmdPad = 6mil
-mdSmdVia = 6mil
-mdSmdSmd = 6mil
-mdViaViaSameLayer = 8mil
-mnLayersViaInSmd = 2
-mdCopperDimension = 15mil
-mdDrill = 6mil
-mdSmdStop = 0mil
-msWidth = 6mil
-msDrill = 13mil
-msMicroVia = 13mil
-msBlindViaRatio = 0.500000
-rvPadTop = 0.250000
-rvPadInner = 0.250000
-rvPadBottom = 0.250000
-rvViaOuter = 0.250000
-rvViaInner = 0.250000
-rvMicroViaOuter = 0.250000
-rvMicroViaInner = 0.250000
-rlMinPadTop = 7mil
-rlMaxPadTop = 20mil
-rlMinPadInner = 7mil
-rlMaxPadInner = 20mil
-rlMinPadBottom = 7mil
-rlMaxPadBottom = 20mil
-rlMinViaOuter = 7mil
-rlMaxViaOuter = 20mil
-rlMinViaInner = 7mil
-rlMaxViaInner = 20mil
-rlMinMicroViaOuter = 4mil
-rlMaxMicroViaOuter = 20mil
-rlMinMicroViaInner = 4mil
-rlMaxMicroViaInner = 20mil
-psTop = -1
-psBottom = -1
-psFirst = -1
-psElongationLong = 100
-psElongationOffset = 100
-mvStopFrame = 1.000000
-mvCreamFrame = 0.000000
-mlMinStopFrame = 3mil
-mlMaxStopFrame = 3mil
-mlMinCreamFrame = 0mil
-mlMaxCreamFrame = 0mil
-mlViaStopLimit = 0mil
-srRoundness = 0.000000
-srMinRoundness = 0mil
-srMaxRoundness = 0mil
-slThermalGap = 0.500000
-slMinThermalGap = 20mil
-slMaxThermalGap = 100mil
-slAnnulusIsolate = 20mil
-slThermalIsolate = 10mil
-slAnnulusRestring = 0
-slThermalRestring = 1
-slThermalsForVias = 0
-checkGrid = 0
-checkAngle = 0
-checkFont = 1
-checkRestrict = 1
-useDiameter = 13
-maxErrors = 50
+description[de] = EAGLE Design Rules\n
\nDie Standard-Design-Rules sind so gewählt, dass sie für \ndie meisten Anwendungen passen. Sollte ihre Platine \nbesondere Anforderungen haben, treffen Sie die erforderlichen\nEinstellungen hier und speichern die Design Rules unter \neinem neuen Namen ab.
+description[en] = EAGLE Design Rules\n
\nThe default Design Rules have been set to cover\na wide range of applications. Your particular design\nmay have different requirements, so please make the\nnecessary adjustments and save your customized\ndesign rules under a new name.
+description[zh] = Seeed Studio EAGLE Design Rules\n
+layerSetup = (1*16)
+mtCopper = 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm
+mtIsolate = 1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
+mdWireWire = 6mil
+mdWirePad = 6mil
+mdWireVia = 6mil
+mdPadPad = 6mil
+mdPadVia = 6mil
+mdViaVia = 6mil
+mdSmdPad = 0mil
+mdSmdVia = 0mil
+mdSmdSmd = 0mil
+mdViaViaSameLayer = 8mil
+mnLayersViaInSmd = 2
+mdCopperDimension = 10mil
+mdDrill = 10mil
+mdSmdStop = 0mil
+msWidth = 6mil
+msDrill = 12mil
+msMicroVia = 12mil
+msBlindViaRatio = 0.500000
+rvPadTop = 0.250000
+rvPadInner = 0.250000
+rvPadBottom = 0.250000
+rvViaOuter = 0.250000
+rvViaInner = 0.250000
+rvMicroViaOuter = 0.250000
+rvMicroViaInner = 0.250000
+rlMinPadTop = 10mil
+rlMaxPadTop = 20mil
+rlMinPadInner = 10mil
+rlMaxPadInner = 20mil
+rlMinPadBottom = 10mil
+rlMaxPadBottom = 20mil
+rlMinViaOuter = 6mil
+rlMaxViaOuter = 20mil
+rlMinViaInner = 6mil
+rlMaxViaInner = 20mil
+rlMinMicroViaOuter = 4mil
+rlMaxMicroViaOuter = 20mil
+rlMinMicroViaInner = 4mil
+rlMaxMicroViaInner = 20mil
+psTop = -1
+psBottom = -1
+psFirst = 0
+psElongationLong = 100
+psElongationOffset = 100
+mvStopFrame = 1.000000
+mvCreamFrame = 0.000000
+mlMinStopFrame = 2mil
+mlMaxStopFrame = 2mil
+mlMinCreamFrame = 0mil
+mlMaxCreamFrame = 0mil
+mlViaStopLimit = 100mil
+srRoundness = 0.000000
+srMinRoundness = 0mil
+srMaxRoundness = 0mil
+slThermalGap = 0.500000
+slMinThermalGap = 20mil
+slMaxThermalGap = 100mil
+slAnnulusIsolate = 20mil
+slThermalIsolate = 10mil
+slAnnulusRestring = 0
+slThermalRestring = 1
+slThermalsForVias = 0
+checkGrid = 0
+checkAngle = 0
+checkFont = 1
+checkRestrict = 0
+useDiameter = 13
+maxErrors = 50
diff --git a/Lighthouse/LED-Strips.brd b/Lighthouse/LED-Strips.brd
new file mode 100644
index 0000000..ded4a5c
--- /dev/null
+++ b/Lighthouse/LED-Strips.brd
@@ -0,0 +1,762 @@
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+<b>PIN HEADER</b>
+
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+>NAME
+>VALUE
+
+
+
+
+
+
+<H3>5050 SMD RGB LED</h3>
+5.0mm x 5.0mm, 2.6mm thickness
+
+
+
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+>Name
+>Value
+
+
+<b>RESISTOR</b>
+
+
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+
+
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+
+>NAME
+>VALUE
+
+
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+
+
+<b>EAGLE Design Rules</b>
+<p>
+Die Standard-Design-Rules sind so gewählt, dass sie für
+die meisten Anwendungen passen. Sollte ihre Platine
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter
+einem neuen Namen ab.
+<b>EAGLE Design Rules</b>
+<p>
+The default Design Rules have been set to cover
+a wide range of applications. Your particular design
+may have different requirements, so please make the
+necessary adjustments and save your customized
+design rules under a new name.
+<b>Seeed Studio EAGLE Design Rules</b>
+
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diff --git a/Lighthouse/LED-Strips.sch b/Lighthouse/LED-Strips.sch
new file mode 100644
index 0000000..e1c1d8d
--- /dev/null
+++ b/Lighthouse/LED-Strips.sch
@@ -0,0 +1,949 @@
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+<H3>5050 SMD RGB LED</h3>
+5.0mm x 5.0mm, 2.6mm thickness
+
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+>Name
+>Value
+
+
+<b>PIN HEADER</b>
+
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+>NAME
+>VALUE
+
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+
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+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
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+>NAME
+>VALUE
+
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+>NAME
+>VALUE
+
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+>NAME
+>VALUE
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+<b>PIN HEADER</b>
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diff --git a/Lighthouse/Lighthouse.lbr b/Lighthouse/Lighthouse.lbr
new file mode 100644
index 0000000..8958715
--- /dev/null
+++ b/Lighthouse/Lighthouse.lbr
@@ -0,0 +1,356 @@
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+
+<H3>5050 SMD RGB LED</h3>
+5.0mm x 5.0mm, 2.6mm thickness
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+>Name
+>Value
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>PIN HEADER</b>
+
+
+
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+>NAME
+>VALUE
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+>NAME
+>VALUE
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+>NAME
+>VALUE
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+>NAME
+>VALUE
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+<b>PIN HEADER</b>
+
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diff --git a/FresseHalten/OSHParkDesignRules.dru b/OSHParkDesignRules.dru
similarity index 100%
rename from FresseHalten/OSHParkDesignRules.dru
rename to OSHParkDesignRules.dru