Added KiCad Project

This commit is contained in:
Nis Wechselberg 2018-06-24 22:40:01 +02:00
parent 6f6b6ea62e
commit 76f7908d3b
6 changed files with 1945 additions and 0 deletions

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# Created by https://www.gitignore.io/api/kicad,sublimetext
### KiCad ###
# For PCBs designed using KiCad: http://www.kicad-pcb.org/
# Format documentation: http://kicad-pcb.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*~
_autosave-*
*.tmp
*-cache.lib
*-rescue.lib
*-save.pro
*-save.kicad_pcb
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv
### SublimeText ###
# Cache files for Sublime Text
*.tmlanguage.cache
*.tmPreferences.cache
*.stTheme.cache
# Workspace files are user-specific
*.sublime-workspace
# Project files should be checked into the repository, unless a significant
# proportion of contributors will probably not be using Sublime Text
# *.sublime-project
# SFTP configuration file
sftp-config.json
# Package control specific files
Package Control.last-run
Package Control.ca-list
Package Control.ca-bundle
Package Control.system-ca-bundle
Package Control.cache/
Package Control.ca-certs/
Package Control.merged-ca-bundle
Package Control.user-ca-bundle
oscrypto-ca-bundle.crt
bh_unicode_properties.cache
# Sublime-github package stores a github token in this file
# https://packagecontrol.io/packages/sublime-github
GitHub.sublime-settings
# End of https://www.gitignore.io/api/kicad,sublimetext

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EESchema-DOCLIB Version 2.0
#
#End Doc Library

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(kicad_pcb (version 4) (host kicad "dummy file") )

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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# 310401X
#
DEF 310401X DS 0 40 Y Y 1 F N
F0 "DS" -500 350 39 H V C CNN
F1 "310401X" 400 350 39 H V C CNN
F2 "" 50 -50 39 H I C CNN
F3 "" 50 -50 39 H I C CNN
DRAW
S -550 -300 550 300 0 1 0 N
P 2 0 1 0 -300 0 -150 0 N
P 2 0 1 0 -50 0 100 0 N
P 2 0 1 0 200 0 350 0 N
P 5 0 1 0 -150 150 -300 150 -300 -150 -150 -150 -150 150 N
P 5 0 1 0 -50 150 -50 -150 100 -150 100 150 -50 150 N
P 5 0 1 0 200 150 200 -150 350 -150 350 150 200 150 N
X E 1 50 -500 200 U 50 50 1 1 I
X D 2 -50 -500 200 U 50 50 1 1 I
X DP 3 350 -500 200 U 50 50 1 1 I
X C 4 -150 -500 200 U 50 50 1 1 I
X G 5 250 -500 200 U 50 50 1 1 I
X ~ 6 -750 -150 200 R 50 50 1 1 N
X B 7 -250 -500 200 U 50 50 1 1 I
X Dig3 8 -750 -50 200 R 50 50 1 1 I
X Dig2 9 -750 50 200 R 50 50 1 1 I
X F 10 150 -500 200 U 50 50 1 1 I
X A 11 -350 -500 200 U 50 50 1 1 I
X Dig1 12 -750 150 200 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# S3F94C4
#
DEF S3F94C4 U 0 40 Y Y 1 F N
F0 "U" 650 550 60 H V C CNN
F1 "S3F94C4" 500 -550 60 H V C CNN
F2 "" 0 0 60 H I C CNN
F3 "" 0 0 60 H I C CNN
DRAW
S -700 500 700 -500 0 1 0 f
X GND 1 -900 450 200 R 50 50 1 1 W
X P1.0(XIN) 2 -900 350 200 R 50 50 1 1 B
X P1.1(XOUT) 3 -900 250 200 R 50 50 1 1 B
X P1.2(nRESET) 4 -900 150 200 R 50 50 1 1 B
X P2.0(T0) 5 -900 50 200 R 50 50 1 1 B
X P2.1 6 -900 -50 200 R 50 50 1 1 B
X P2.2 7 -900 -150 200 R 50 50 1 1 B
X P2.3 8 -900 -250 200 R 50 50 1 1 B
X P2.4 9 -900 -350 200 R 50 50 1 1 B
X P2.5 10 -900 -450 200 R 50 50 1 1 B
X VCC 20 900 450 200 L 50 50 1 1 W
X (ADC8/CLO)P2.6 11 900 -450 200 L 50 50 1 1 B
X (ADC7)P0.7 12 900 -350 200 L 50 50 1 1 B
X (ADC6/PWM)P0.6 13 900 -250 200 L 50 50 1 1 B
X (ADC5)P0.5 14 900 -150 200 L 50 50 1 1 B
X (ADC4)P0.4 15 900 -50 200 L 50 50 1 1 B
X (ADC3)P0.3 16 900 50 200 L 50 50 1 1 B
X (ADC2)P0.2 17 900 150 200 L 50 50 1 1 B
X (ADC1/INT1/SDA)P0.1 18 900 250 200 L 50 50 1 1 B
X (ADC0/INT0/SCK)P0.0 19 900 350 200 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
#End Library

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update=Mi 20 Jun 2018 09:32:12 CEST
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[general]
version=1
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=858D Reverse Engineering
LibName2=power
LibName3=device
LibName4=switches
LibName5=relays
LibName6=motors
LibName7=transistors
LibName8=conn
LibName9=linear
LibName10=regul
LibName11=74xx
LibName12=cmos4000
LibName13=adc-dac
LibName14=memory
LibName15=xilinx
LibName16=microcontrollers
LibName17=dsp
LibName18=microchip
LibName19=analog_switches
LibName20=motorola
LibName21=texas
LibName22=intel
LibName23=audio
LibName24=interface
LibName25=digital-audio
LibName26=philips
LibName27=display
LibName28=cypress
LibName29=siliconi
LibName30=opto
LibName31=atmel
LibName32=contrib
LibName33=valves
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=60

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